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'ESTIMATES INCLUDE A LOAD AND STORE WHICH REQUIRE ABOUT 13 in: MULTIPLY OR DIVIDE BY POWERS OP 3 TAKES APPROXIMATELY (»IB-TENTH THE NOMINAL MULTIPLICATION TIME.

"ESTIMATES ARE FOR R EG 1ST EH-TO-REGISTEH ONLY.

'ESTIMATES INCLUDE A LOAD AND STORE WHICH REQUIRE ABOUT 13 in: MULTIPLY OR DIVIDE BY POWERS OP 3 TAKES APPROXIMATELY (»IB-TENTH THE NOMINAL MULTIPLICATION TIME.

"ESTIMATES ARE FOR R EG 1ST EH-TO-REGISTEH ONLY.

NSSC-I. This computer uses 18-bit words and fixed point, two's complement arithmetic. A 55-instruction set is available with a basic cycle time of 1.25 ¡is and a 5-/is requirement for an add operation. (These values are still uncertain and may be revised in subsequent versions of the computer.) A detailed description of the instruction set is given by Merwarth [1976].

A set of mathematical subroutines for the NSSC-I has been designed to provide elementary 18- and 36-bit operations [DeMott, 1976]. Timing estimates for these are given in Table 6-14. The efficiency of coding the NSSC-I is limited because it has only three registers: an accumulator and an extended accumulator (which are combined into a double-length register for products and dividends in multiplication and division) and one index register. A further complication is introduced by the small word size which allows only 12 bits for operand addresses in instructions. The NSSC-I therefore uses a page register to specify the logical bank, or 212 = 4096 word* region, from which the operand is to be retrieved. Loading, reloading, and (especially) saving and restoring the page register is cumbersome, so NSSC-I programs can address directly only 4096 words of data and only data defined within the independently assembled module which addresses it.

An interrupt system provides 16 hardware interrupts and one programmable intemipt. Input and output are provided from 16 devices [Merwarth, 1976]. The onboard computer transmits data to the ground at the rate of one word per telemetry frame (see Chapter 8) and receives commands at the rate of 2000 bits per second (a 48-bit command every 24 ms). Memory dump, via S-band, is available at 32,(X)0'bits per second.

Memory for the NSSC-I is expandable in 8192 word modules to a maximum of 8 modules. Hardware protection against changing data or instructions within selected address limits is provided. The proposed memory layout for MMS is shown in Fig. 6-51. A flight executive is used to schedule the various tasks of the onboard computer. These tasks include high-priority attitude control operations (probably every 128 ms for SMM) in addition to low-priority housekeeping functions. The latter include performing functions normally provided by analog devices such as thermostats and other spacecraft hardware.

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