A New Camera For Emccds

We have developed a new camera specifically for driving EMCCDs at pixel rates up to 35 MHz in photon counting mode. There is considerable variance in the amplitude of each photon event. This relaxes the requirement to design very high precision electronics compared to driving a conventional slow-scan wide dynamic range camera. Our design uses a Kodak KSC-1000 sequencer that provides control flexibility at pixel rates of 4-60 MHz. We have used the latest integrated circuits developed for commercial digital camera use extensively. These include high-speed clock drivers and integrated CCD signal processors that provide preamplifier, double correlated sampling, and analogue to digital conversion in a single low-cost package. Generally we have found the performance of these devices to be extremely good.

The most novel aspect of an EMCCD controller design is the high-voltage clock driver. The e2v technologies devices require a voltage swing in excess of 40 V. The manufacturers suggest using a sinusoidal driver which can be designed to minimise power consumption. However, such a circuit needs to operate continually, which is not simple unless it was designed in association with the sequencer architecture. The other possibility is to use a switch circuit. Figure 1 shows the general layout we have found successful. It is essential that the two enhancement mode FETs are closely matched. If the two transistors are turned on simultaneously for only a nanosecond the currents are extremely high, causing components to emit a lot of noxious smoke. This schematic uses some of the components and structure suggested on the datasheet for the Texas Instruments TC285 Impactron device. Note, however, that their suggested transistors are not very well matched causing the circuit to perform less well than expected. The devices shown in Figure 1 are manufactured by Vishay-Siliconix. Careful attention to layout and thermal management is essential. The schematic shown provides a 40 V square wave with a rise time of 12-15 ns.

Figure 1. The schematic of the high-voltage clock driver used for EMCCDs in the present controller design.

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