Architecture

The CCD controller consists of four boards: an interface and timing board, a clock driver board, a video processor and bias board, and a board to mount the CCD (see Fig. 1). Typically, these boards would be stacked on top of each other using the PC104 ISA bus connector, which is only used here to bus power between the boards.

Clock driver board

Clock driver board

Figure 1. Architecture of the HIAC controller. Each large block represents an individual board module in the PC104 stack.

The interface board uses an Altera Acex FPGA operating at 100 MHz to generate the CCD clock sequences (see Fig. 2). Cypress's FX2 chip is used to implement the USB 2.0 interface to the FPGA and to the output port of the ADC on the video-processor board. The FX2 has a built in 8051 microcontroller that is only used to interface the FPGA circuit to the USB.

The video board uses an Analog Device, AD9814 CCD signal processor to perform correlated double sampling and effectively 13.5 bit digitization of the CCD signal at 7 MHz. The video board also provides 11 programmable fixed bias lines for operating the CCD and a programmable supply for running a Peltier element. Each clock board provides 11 clocks with levels between -10V and +10V and a single clock with a range of -10V to +48V. Up to two clock boards can be incorporated in the system. The CCD board contains no active components, serving only to mount the CCD and clock line terminations.

Moveable Partition Wall Dimensions
Figure 2. Simplified schematic of the FPGA clock sequencing circuit. The circuit allows the user to switch quickly between different clocking sequences.

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