All functions are based on the XILINX Virtex Pro FPGA XC2VP7 FF 672. The back-end is a 64 Bit PCI board (see Fig. 2). The FPGA contains the PCI interface for communication functions, the video data DMA channel and the RocketIO transceivers for link transfer. The interface from PCI to FPGA does not have glue logic. PCI master (data) and PCI slave (communication) interfaces are independent and can work concurrently. All communication and data transfers are on serial links. Scatter /Gather DMA is used for data taking, all communication runs with a handshake protocol.

Figure 2. Back-end block.


Figure 3. Front-end basic block.

All functions are based on the XILINX Virtex Pro FPGA XC2VP7 FF 672 (see Fig. 3). The FPGA contains the link interface for communication and data transfer with RocketIO transceivers, sequencer, system administration, interface to acquisition, clock and bias, telemetry and monitoring. The board contains four ADC channels (with 16- or 18-Bit Analog Devices Pulsar ADCs), 16 clocks and 20 biases, all remotely programmable, Telemetry with 16-Bit accuracy, monitor outputs of video input, ADC input, clock signals, convert strobe and digital marker signals. There are galvanic isolated trigger input and control output signals. LVDS signals are provided to connect to detector ASIC's - all communication and data transfer to the back-end is handled with the same firmware used for conventional detector read-out.

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