Basic CCD Structure

Figure 1 depicts the basic elements of an n-channel, back-illuminated CCD; for p-channel CCDs, which have such advantages as greater resistance to space radiation, the labels "n-type" and "p-type" in Fig. 1 are interchanged. The starting material is a p-type wafer typically 600-700 ^m thick. The n-doped buried channel region at the upper surface is typically no more than 0.1-0.2 ^m thick. Photoelectrons are collected and transported to an output circuit within this layer. Its most important function is to ensure that the electrons are kept away from the Si/SiO2 interface where they could otherwise be trapped by surface states. The wafer surface has a thin layer of SiO2, and sometimes an additional layer of Si3N4, which serves as a gate dielectric, and on top of this layer is a set of electrodes or gates that control the collection and transport of the photoelectrons across the device.

Figure 1. Depiction of the cross section of a three-phase CCD viewed (left) across the device gates and (right) parallel to the device gates.

After device fabrication the wafer must be thinned from the back surface to a final thickness typically 10 ^m up to 300 ^m to enable the CCD to be illuminated from the back. Such so-called back-illuminated devices offer the ultimate in high QE, as will be seen in Section 3, in contrast to conventional CCDs illuminated from the front or circuit side, which suffer from substantial reflection and absorption losses in the gates and dielectric layers. The back surface, however, must be carefully treated to avoid loss of photoelectrons to surface states or traps, and this usually means that a heavily doped p-layer (labeled p+ in Fig. 1) is introduced into the back surface. An antireflection coating on this surface is also required for highest QE.

The process by which an image is formed is as follows. Photons incident on the back surface of the device create electron-hole pairs. The photoelectrons are collected by electric fields set up by the CCD gates in packets in the buried channel under the gates with high potentials (Vhigh in Fig. 1), and the neighboring gates at lower potentials (Vlow) provide electrical isolation of the packets. For a three-phase device, each set of three gates defines a pixel along the direction of charge transport. Charge packets are transported from gate-to-gate by applying a set of time-varying waveforms to the gates.

In the cross-sectional view of a CCD taken in a direction perpendicular to the charge-transfer direction, shown in Fig. 1 (right), the important feature is the channel stops that define the left and right boundaries of a pixel or CCD channel. Typically, these are heavily doped p-type regions, and often the SiO2 here is thicker than the gate dielectric. The channel stops terminate the edges of the channel. In later sections we will see how modifications of the channel stops are used in two advanced features of CCDs.

An important feature in understanding the image resolution of a CCD is the depletion layer. A depletion layer is depicted in Fig. 2 in the upper portion of the p-substrate and the n-buried channel. Here, the fields due to the CCD gates and the buried channel combine to remove the holes to a depth, called the depletion depth, that depends on the gate biases and the resistivity of the p-substrate. In this region the vertical component of the electric field is sufficiently strong to pull photoelectrons fairly quickly (a few ns) into the CCD channel. In the undepleted or neutral portion of the substrate near the back surface, photoelectrons may wander by thermal diffusion over substantial distances before they reach the depletion layer boundary and are swept into the channel. This process clearly degrades imaging resolution, and thus back-illuminated devices must be operated under nearly or fully depleted conditions.

Figure 2. Cross section of a CCD depicting the depletion layer and the neutral undepleted layer at the back surface and its effects on photoelectron charge collection.

As we will see later in Section 3, it is extremely desirable to make CCDs as thick as possible in order to maximize QE in the near infrared (^~700-1000 nm), where photon absorption depth becomes progressively greater and thicker devices are needed to absorb the photons. However, this makes fully depleted operation more difficult.

What are the factors that enable deep depletion depths in a CCD? Raising the gate biases increases the depletion depth, but this approach has its limitations because the higher fields across the device oxide layers lead to spurious charge generation and eventually to catastrophic dielectric breakdown. Another approach is to use lightly doped or high-resistivity substrate material, since depletion depths vary as Na1/2, where Na is the doping concentration of the substrate (resistivity varies as 1/NA). Typical scientific CCDs are made on material having resistivities of the order of 100 Q-cm or less, resulting in depletion depths of only about 15-20 ^m. For better results, some CCDs are made on special material having resistivities of several thousand Q-cm resulting in depletion depths of 60 ^m or more.

The deepest depletion is obtained by combining high-resistivity substrates with a bias applied to the back surface. This approach has been used, for example, by the Lawrence Berkeley National Laboratory group to produce fully depleted p-channel CCDs that are more than 300 ^m thick [3].

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