The first buffer stage for the CCD outputs is a cascode stage with two low noise JFETS Q1 and Q2 (see Fig. 3). Q1 acts as a source follower with a gain slightly below 1. Because the resistors R1 and R2 are equal, the signal voltages across R1 and R2 are also equivalent, but with opposite phase. R3 and R4 provide the DC bias for Q2. The advantage of this circuit is a gain two times higher when compared with a single buffer stage. As a benefit the circuit delivers a differential output signal. L1 is a common mode choke to improve noise immunity. Q3 is the usual JFET current source to set a proper load current (1 to 2.4 mA) on the CCD output.
The subsequent video processing stage consists of a differential input amplifier with a line clamp circuit. Further video signal processing methods are currently under investigation. Options under consideration are:
Classical clamp-and-sample, similar to the circuit used in FIERA , where the sampling is actually performed by the Analog-to-Digital Converter (ADC).
Sample-hold stage with a subsequent differential amplifier to subtract the sampled reference level from the signal level. The resulting signal is then sampled and converted by the ADC.
Sampling of reference and signal level with the same sampling ADC and subtraction by software (Digital Double Sampling).
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