In the early days of CCD development at LBNL, fabrication was done in-house in a Class 10 clean room using 100 mm diameter wafers. Figure 2 shows such a 100 mm wafer containing a 2K*4K, 15 ^m pixel size CCD and other smaller devices. CCDs fabricated at this facility are currently in use at ground-based observatories.
The processing steps critical to the fabrication of LBNL CCDs and the challenges in implementing them have been described in some detail in Holland, et al.  and Bebek, et al. . In summary, they include completion at the full wafer thickness of all front-side processing up to the aluminum contact mask step. Then the wafers are ground and polished to final thickness of 200-300 |m. They are then back-side finished with an In-Situ Doped Polycrystalline silicon (ISDP) process at 650°C making an extremely thin ohmic contact for biasing. The ISDP formation process temperature is too high for Al so the contacting and metallization is done afterwards.
With the advent of the proposed SNAP it became clear that the large number of devices required for this and other applications would require the services of an outside fabrication vendor. DALSA Semiconductor was selected. Since DALSA uses 150 mm wafers, new design formats were needed. Figure 2 shows a 150 mm wafer with three SNAP style version-0 CCDs and two 2K*4K, 15 jim CCDs. Two different pixel sizes 10.5 |m (28802) and 12 |m (25202) were chosen for the SNAP version-0 devices to accommodate early SNAP design requirements.
When the decision to outsource fabrication was made, the entire process was initially planned to be executed by DALSA. It was found, at an early stage, that significant process development would be required to work with the thinned 150 mm wafers. As a result, a business model was developed in which DALSA does front-side processing up to the contacting step. LBNL then finishes the processing using clean room equipment upgraded to 150 mm wafer capability using good quality used equipment. While a number of difficulties were encountered initially , recent results are very promising. A significant advantage of the business model is that the processing necessary for back illumination is done at the wafer level, which results in a technology that is amenable to volume manufacturing.
In addition to the business model described above, two other approaches have been followed. These include the use of a refractory metal alloy (a Ti/TiN stack) instead of the standard aluminum interconnects. This material can withstand the ISDP process at 650°C so the front-side can be fully completed at DALSA before thinning and back-side finishing. Although the TiN has higher resistivity than Al, good results have been obtained .
As a second alternative process we are collaborating with researchers at the Jet Propulsion Laboratory (JPL) to apply delta doping to p-channel CCDs. Molecular beam epitaxy is used to form the backside ohmic contact layer. This is a low-temperature process that grows a thin layer of Sb-doped silicon at temperatures not exceeding 450°C, thereby permitting Al interconnects to be fabricated before thinning. This process is still under development  but continues to look promising, especially for UV-enhanced detectors.
As the SNAP proposal evolved, further refinements in science requirements led to the specification of a pixel size of 10.5 |m together with a PSF of 4 |m rms. In addition, larger pixel counts were required. PSF measurements on the version-0 devices showed that this requirement could not be met without going to higher substrate voltages than version-0 was designed to accommodate. The version-0 devices were normally 250 | m thick and could safely withstand about 50 V of bias while PSF measurements and modeling predicted a need for 200 | m devices biased to 80 V. Figure 3 shows measured PSF data for 200 and 280 |m CCDs as a function of substrate voltage (Karcher, et al,  with additional measurements by J. Fairfield).
An analysis of breakdown conditions in the version-0 devices led to a number of design enhancements resulting in the version-1 CCDs. The wafer, shown in Fig. 4a, contains four version-1 devices, all with 3512*3512, 10.5 | m pixels and various design modifications together with other smaller test CCDs. More than 36 of the SNAP devices were fabricated (some un-thinned, some with the business model processing and some with TiN contacting), mounted and tested to determine performance. Most of the thinned CCDs with the high-voltage enhancements withstood voltages well in excess of 80 V. Some of the un-thinned devices withstood over 200 V of bias without any noticeable breakdown or "glow". There were some problems observed in some of the CCDs in which the signal baseline values were unstable and tended to drift under certain bias voltage and exposure conditions.
A detailed analysis of the results was made and new simulation models were introduced to explain the observed behavior. Armed with these improved models, the current SNAP version-2 CCDs were designed. These were fabricated on the wafer shown in Fig. 4b, containing four devices of the same pixel count and size as the version-1.
2.4 Version-2 Device Test Results
The version-2 design was submitted to DALSA in early 2005 and the first wafers were received in March. These were proof devices fully finished with Al metallization, ready to be tested un-thinned with front-illumination. All version-2 CCDs were wafer probed at -45°C and tested for functionality prior to dicing. This was done at UC Lick with the help of Richard Stover and will soon be performed at LBNL when our own wafer prober commissioning is complete. Of 16 devices, about 80% were functional, and after mounting, most of those tested were found to perform well in our test dewar operated around 140 K.
An important goal of the version-2 design is to achieve reliable operation at the SNAP-required substrate voltage Vsub = 80 V. To test this, CCD performance was evaluated at voltages significantly higher than required. For example, Fig. 5 shows an 1800 second dark exposure of one of the un-thinned CCDs operated at Vsub = 206 V. At this voltage the CCD is fully depleted even though it is 650 ^m thick. This can be seen by examining the cosmic ray tracks. Incomplete depletion leads to puffy track ends from diffusion in field-free regions. No evidence of "glow" or any other signs of breakdown were observed, and in fact, the dark current measured for this image was determined to be 0.63 e-/pixel/hour.
Figure 5. 1800 second dark exposure of a 650 ^m thick front illuminated CCD operated fully depleted at Vsub = 206 V.
To measure gain and Charge Transfer Efficiency (CTE), x-rays from the radioactive source 55Fe are used . Figure 6a shows the x-ray histogram obtained from such a measurement of a different front-illuminated version-2 CCD operated at Vsub = 107 V. The well resolved Ka and Kp x-ray peaks indicate good performance. The read noise for this CCD was 3.6 e- rms (at 70k pixels/sec). In Fig. 6b is shown the parallel stacking plot for the same measurement. This and the corresponding serial plot yielded a serial CTE = 0.999 999 75 ±1.4x10"7 and a parallel CTE = 0.999 999 88 ± 1.2X10"7.
In addition to the full wafer thickness front-illuminated CCDs, a number of thinned and finished devices have been produced according to the business model and screened with wafer cold-probing (over 40, 200 ^m thick CCDs to date). At the time of writing, only a couple of the SNAP version-2 CCDs have been tested. The promising results so far are illustrated in the projected test image shown in Fig. 7.
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