Circuit Overview

Vref

Input

Vref

Input

Data Out

Figure 1. The block diagram of the CRIC II chip.

Data Out

Figure 1. The block diagram of the CRIC II chip.

The circuit consists of four major components, which can be seen in Fig. 1:

• The input stage with preamplifier and single-ended to differential conversion.

• The signal processing stage with its Correlated Double Sampler (CDS).

• The band-gap based voltage reference for both the input stage and A/D.

2.1 The Input Stage

The CCD will be AC coupled to the readout chip with a large external capacitor. This is necessary to eliminate the influence of the parasitic capacitance of the input node due to ESD protection circuitry. To charge this capacitor to its operating voltage upon CCD power-up, the CRIC II has a dedicated input clamp switch that connects its input to the voltage reference with a low resistance. After power-on, the switch is disabled.

During normal operation, two other switches control the input signal. One switch disconnects the input during CCD clocking transitions to prevent amplifier saturation. The last switch is responsible for setting the DC operating point of the input amplifier. During the sampling of the CCD reset level, this switch is closed. It connects the input to the reference voltage through a large (200 kQ) resistor. Together with the input coupling capacitor, this resistance creates a time constant for change of the input voltage that is much longer than a single pixel sampling time. Since the CCD reset level is independent of the CCD signal, averaging over the reset level only creates a consistent DC baseline for the signal processor.

The central part of the input stage consists of an ultra low noise preamplifier with a gain of four. The gain is chosen to minimize the noise contribution of downstream system components, while maintaining a large dynamic range using only 3.3 V operating voltage. The opamp input is biased at 200 ^A to achieve a thermal noise spectral density of about 4 nV/Hz1/2. The output settling time to 16-bit linearity is about 200 ns. The input stage is one of the main power consumers of the chip, but lower power can only be achieved at the price of higher noise. The output of the first stage is connected to a unity gain inverter, generating a differential signal of 2 V from a 500 mV full-scale CCD signal input, effectively doubling the available dynamic range.

2.2 The Correlated Double Sampler

It has been shown [2] that a dual slope integrator is efficient at eliminating reset transistor noise, and also attenuates noise that is significantly higher or lower in frequency than the CCD pixel rate. Such a dual slope integrator integrates the reset signal level at one polarity and then integrates the image signal level at the opposite polarity, in effect subtracting the reset level from the pixel signal level. Since the input stage already generates a differential signal, changing the polarity of the input signal for the integrator merely requires a cross-over switch. Care has to be taken that the resistive miss-match of the switch is much smaller than the integration resistor (see Fig 1.) to obtain the full benefit of the CDS noise rejection.

The gain of the integrator is directly dependant on the value of the integration resistors, while the input stage gain is dependant only on the ratio of feedback resistors. Therefore, the integration resistors require particular attention to reduce the temperature coefficient.

2.3 The Multi Slope Integrator

The dynamic range requirement is 16-bit, derived from 2 electrons CCD readout noise and 130K electrons full well capacity. The requirement for the signal to noise ratio, however, is driven by the Poisson process of the light interacting in the sensor, which has a variance equal to VN, where N is the number of incoming photons [3]. The signal can be digitized with an LSB size that depends on the signal amplitude such that the A/D quantization noise is still below the Poisson noise, allowing the implementation of a dynamic range compression without the loss of data. Since the implementation of a radiation tolerant 16-bit A/D converter in the required power budget seemed unrealistic, a means of dynamic range compression had to be adopted. The CRIC II chip is intended for use in high precision photometry, so the compression scheme has to allow for simple yet precise calibration.

In the CRIC chip a novel compression was implemented; the integrator has three integration capacitors. Initially only the smallest capacitor is connected. A comparator at the integrator output triggers a flip-flop if the voltage on the integration capacitor rises above a set-point. This switches in an additional larger capacitor. A third capacitor can be switched for larger signals. Fig. 2 shows the signal at the output of the integrator for a signal close to full-scale. Traces two and three show the flip-flop outputs that drive the gain selection. These two gain bits are transmitted along with the A/D conversion result for each CCD pixel to allow full reconstruction of the image signal.

There are several advantages of a multi-slope integrator over a logarithmic gain amplifier for dynamic range compression. A non-linear preamplifier requires extensive data sets for gain and offset calibration, and radiation induced parameter shifts will likely require on-orbit recalibration. For the multi-slope integrator this is much easier. When the second gain stage is triggered and the additional capacitor is turned on, the charge stored on the integration capacitor is redistributed and none of it is lost. Additional charge injection from switching is carefully eliminated. This means that in each section the gain is different, yet they all share a common offset. To fully characterize the system one needs only two points in the first slope to determine its gain and offset, then one point each in the following slopes to determine their gain.

In Fig. 3 the noise margin between the photon shot noise on the CCD and the quantization noise due to the bit size of the A/D converter is shown. The plot also demonstrates the advantage of a multi-slope integrator followed by a 12-bit A/D over a standard linear 16-bit converter for small signals. Since the dynamic range of modern CCDs is often greater than 16 bits, a linear converter is forced to a larger number of bits or to undersample the read noise.

Figure 2. A large signal on the auto-gain integrator.

Figure 3. Comparing shot noise and quantization noise.

2.4 The Pipeline A/D Converter

To sample the output of the multi-slope integrator a 13-bit A/D converter has been implemented. We chose a 13-bit range with a fixed negative offset of 4K electrons to eliminate the need to remove the CCD offset voltage. The range of the 13-bit A/D converter is adequate to fully sample the CCD output signal, and any offset subtraction can be done later in the digital domain.

After studying several A/D architectures, we decided on pipeline architecture for the CRIC II chip. This architecture achieves high resolution while maintaining low power consumption. It also has the advantage of 12 identical stages, greatly reducing layout efforts. Pipeline A/D converters have excellent linearity by design, as can be seen in the test results section. To prevent the digital noise from degrading the signal, the A/D converter is clocked at pixel read rate and the timing is designed so that no transitions occur during either integration period. Since any digital noise is generated while the integrator is off, such noise is completely rejected.

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