Cmos Fabrication Processes

The attraction of CMOS-based process technologies for imaging applications is that they can bring control electronics and a sophisticated range of signal processing tools in very close proximity to the focal plane. Still, CCD fabrication methods have been steadily optimized over the past 35 years to produce large-format devices with broad spectral response, low noise readout, and good yield. In this section we compare the process technologies used for CCD- and CMOS-based imagers and describe why the newest advancements in CMOS processes offer some attractions for highperformance imaging.

5.1 CCD vs. CMOS Fabrication Process Comparison

CCD imagers are generally fabricated on 125-mm silicon substrates in facilities that are "trailing" in feature-size advancements relative to the most aggressive CMOS foundries. The circuits fabricated in CMOS-based process technologies benefit from improvements encouraged by a wide-scale demand for fast, compact, low-power electronics. The concurrent economics of scaling wafer size up and feature size down propel frequent migrations to new technology "nodes," which correspond to logic speed improvements. Many CMOS foundries are routinely processing 200-mm wafers, with the newest facilities now handling 300-mm wafers, and most research laboratories using 150-mm wafers. Commercial ventures benefit from wafer size increase because the cost per chip generally goes down, but even research efforts are eventually forced to migrate up in wafer size because of the availability of high-quality substrates and advanced deposition, etch, and lithography tools.

Manufacturers of CCDs may eventually feel this pull as well, though presently the very high resistivity float-zone silicon substrates (5000-7000 Q-cm) required for deep depletion and good spectroscopic performance at long wavelengths are only available up to 200-mm diameter, and the commonly used full-wafer lithography tools are not yet available for the larger wafer sizes. Since float-zone silicon is vulnerable to the generation of plastic slip and dislocations and requires special processing techniques that limit thermally induced stresses during high-temperature processes [6], migrating a science-grade CCD process technology to an even larger wafer size would require reassessment of all thermal processing as well as design/layout methods to minimize stresses induced by multiple layers of patterned polysilicon crossing channel stops.

In its highly evolved present state, the common implementation of a CCD imager structure does produce a satisfactory yield of millions of active elements in a single device. The buried-channel structure, multiple oxidation cycles, and composite gate dielectric are all engineered to have superior charge transfer efficiency, noiseless operation (until readout), and resistance to interpoly and substrate shorts. However, CCDs generally require clocks of at least 10 V to maintain sufficient charge capacity in the well. These 10-V clocks are incompatible with the 1- to 5-V levels necessary for low-power on-chip circuitry. Shallower CCD buried channels and thinner gate dielectrics can produce imagers that operate at lower voltages [7], and such improvements have the greatest benefit if accompanied by on-chip access to digital logic gates as well.

Most mixed-signal CMOS technologies easily support implementation of single chip designs with multiple operating voltages, for example, to manage dynamic range and power. A further aid to the circuit designer is the presence of several levels of interconnect metal (typically five to seven), which permits great flexibility in routing methodology. The highly nonplanar structure of a CCD hampers reliable patterning and isolation of even one or two levels of metal interconnect. An extreme case of this is seen in Fig. 12, which presents an early optical micrographic view of the four-poly pixel array and a scanning electron cross section through the pile-up of layers that cross the channel stop. Each reentrant edge seen is a vulnerable spot for interpoly shorts and a trap for hidden metal shorts.

Ccd Cross Section
Figure 12. Optical photomicrograph and cross section through channel stop region of four-poly orthogonal-transfer CCD (OTCCD).

The structure of CMOS devices can be appreciated in the scanning electron micrographs of Fig. 13, which provide a detailed view of a five-transistor SRAM cell and a cross section through three interconnect metal layers with planarized interlevel dielectrics.

Manufacturers of CCDs are choosing to implement some of these CMOS-developed processes when appropriate, but one remaining comparison is architecturally, rather than process, driven—the repetitive transfer of charge packets through the silicon lattice in a CCD causes the device to be vulnerable to space-radiation-induced traps. CMOS-based active pixel imagers require few to no charge transfers and can readily adopt a number of design and process hardening methods to yield science-grade imaging sensors that are suitable for long-term space-based applications.

5.2 CMOS Technology Features and General Limitations of Monolithic Imagers

CMOS device size and voltage scaling are driven by logic applications that demand ever-faster computation with reduced power dissipation. In each generation of fabrication technologies a number of process features change, as detailed in Table 3. For example, the local oxidation process (LOCOS) used for device isolation in both CCD and larger-geometry CMOS technologies is replaced by a more compact shallow trench isolation (STI) process that permits much higher circuit layout densities and better junction isolation.

To produce the same transistor channel inversion charge the lower operating voltage requires higher gate capacitance, and so the gate dielectric is made thinner and nitrogen may be introduced to inhibit dopant penetration from the gate into the silicon channel. For high transistor on-state current with well-behaved off-state current, the shallow device junctions have sharply defined doping profiles fixed by rapid thermal activation of the extension and source/drain implants.

However, many of the process modules that become standard for highly scaled CMOS, such as STI, thin gate dielectric, and silicided junctions, introduce additional sources of device and junction leakage, and the optically opaque silicides can block photoabsorption in the silicon. While anisotropic physical profiles are obtained with now-common plasma (dry) etch processes, the surface damage created may not be repaired within the strict thermal budget. Even low levels of surface damage or stress-induced stacking faults like those seen in Fig. 14 can create leakage that contributes to dark current.

Figure 13. (left) Silicon-on-insulator (CMOS) 180-nm SRAM cell and (right) three levels of metal stacked with vias to poly.

To support the fabrication of low-cost CMOS image sensors for consumer applications, many CMOS logic foundries now offer special steps that protect the sensitive pixel transistors from some of the most damaging exposures. The process flow shown in Fig. 15 [8] illustrates how pixel transistors are coated with an additional oxide layer, which is etched back and patterned to permit silicide formation only on the gate polysilicon and on the source/drain regions of peripheral devices.

Table 3. Summary of CMOS Process Technology Features.


0.35-0.60-^m Gate Length

0.18-0.25-^m Gate Length



Operating voltage

3.3-5 V

1.8-2.5 V

Field isolation


Shallow trench isolation

Gate oxide

70-125 A

32-50 A

Gate dielectric

Silicon dioxide

Nitrided silicon dioxides

Junction profile

Graded junction

Shallow junction

Thermal budget

Furnace anneal

Rapid thermal processing

Spacer etch

Oxide spacer

Silicon nitride spacer



Self-aligned silicide


Spin-on-glass and reflow

Chemical mechanical planarization

Figure 14. Cross-sectional transmission electron micrograph of pixel. From Wuu et al. [8].

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