Design

The design (see Fig. 1) is a 24 ^m square 240^240 pixels split frame transfer 8-output back illuminated L3CCD, designated as the CCD220. The shuttered variant is designated as the CCD219.

Figure 1. Schematic of CCD220.

The image and store area are built with metal-buttressed parallel clock structures to enable line shifts of 10 Mlines/s for a total transfer time of 12 ^s from image to store, and low smearing of under 1.5% at 1,200 fps. Two phase clocking was chosen for simplicity, lower power dissipation, and symmetry of drive. See Gach et al. [4] for a discussion of the benefits of a symmetric drive for the CCD controller.

The store area is slanted to make room for the standard serial registers (three phase clocking) to curve around (see Fig. 2) and provide space for the output circuitry. Each output will have a 520 element 16 ^m standard L3Vision gain register whose gain is controlled by the voltage of the multiplication phase. The output amplifier will be single stage (see Table 1) and of similar design to that employed on recent L3V CCDs. The gain register and output amplifier will be optimized for a gain of 1000, a value typically expected for AO applications, to provide an overall effective read noise of under 0.1e-. The serial registers, gain registers, and output amplifiers are designed to operate up to 15 Mpixel/s to achieve a full goal frame rate of over 1,500 fps.

Table 1. Specifications of output amplifier.

Feature

CCD220

Table 1. Specifications of output amplifier.

Feature

CCD220

Overall responsivity

Node capacitance

Reset rms noise (dominates without CDS)

Saturation (3 V swing at node)

Output impedance

Maximum frequency (settling to 1%)1 Maximum frequency (settling to 5%)

1.7 ^V/electron 57 fF

45 electrons 100 electrons 1.0M electrons 350 Ohms 15 MHz 25 MHz

The baseline device will be built in standard silicon and is low risk with guaranteed delivery of devices that meet minimum requirements. This meets the risk profile of both JRA2, who must produce a design report to the EU on a 2-3 year timescale, and ESO, who require working detectors for their next generation of instruments. A split wafer run will enable the production of two speculative variants. The first will build devices in deep depletion silicon offering much improved red response. High red response is important for applications that rely on natural GS such as VLT Planet Finder. The second is to build devices with an electronic shutter to extend the use of the detector to applications such asRayleigh Laser Guide Star (RLGS), which require very short shutter times of ^s. These short shutter times are not

1 Load capacitance (external and package) <10 pF

possible by mechanical means. RLGS systems can offer substantial savings in costs and development efforts in that they can use commercially available pulsed lasers as opposed to specialized sodium lasers.

No dump gate was included in the design as it was doubtful whether its response time to dump charge would be faster than simply clocking the serial register. It was also a concern if it would add excessive capacitance to neighboring registers and add pins to the package resulting in a larger package size and more heat load. Additionally, for deep depletion devices a much wider dump gate would be required to avoid parasitic effects resulting in an even slower dump time.

As well reducing pin count, summing wells were not included because with low read noise of 0.1e- binning could easily be performed off chip.

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