Electronic Shuttering

Mechanical shutters are a perennial problem for astronomers, all the more so in this era of ever larger focal-plane arrays (FPAs). Thus, an electronic solution to this problem would seem to be enormously attractive. Interline-transfer devices have an effective shuttering capability but only for front-illuminated formats where the charge can be shifted into the readout registers that have been covered with a thin-film light shield.

An electronic shuttering feature for back-illuminated CCDs has been demonstrated by Reich et al. [21] on small imagers intended for adaptive-optics applications but so far not demonstrated on large-scale devices. The modifications to the device needed to implement the shutter are depicted in Fig. 22.

n+ shutter drain Gate n+ shutter drain Gate stop stop

Shutter implant

Figure 22. Cross-sectional view of a CCD with the principal features needed for the electronic shutter.

Two new features have been added to the pixel. The first is a deep p-type implant, called the shutter implant, which lies about 2.5 ^m below the surface. This layer creates a potential barrier to photoelectron flow from the back surface, which can be modulated by the gate voltage. The second feature is an n+ region within the channel stop whose function is to collect photoelectrons when the shutter is closed. The shutter operation is illustrated in Fig. 23.

Figure 23.

Operation of the shutter: (left) gate voltage is high and the shutter drain low, allowing photoelectrons to be collected; (right) gate voltage is at a lower setting for readout and the shutter drain high.

To open the shutter the imaging-array gates must be set to a relatively high potential, typically 18 V. The E-field set by the gate overcomes the potential barrier established by the shutter implant, and the depletion region is pushed all the way to the back surface. At the same time the shutter drain is biased to a relatively low potential. Under these circumstances all the photoelectrons are collected in the CCD wells. To close the shutter and read out the integrated charge the imaging gates are returned to lower levels, typically <8 V for the high state, in which case the depletion layer collapses to the depth of the shutter implant. To collect photoelectrons while the shutter is closed, the shutter-drain potential is raised to the point where it establishes its own depletion layer and collects photoelectrons.

An important performance metric for the electronic shutter is the extinction ratio, that is, the fraction of photoelectrons collected when the shutter is off. This is principally a problem in the near infrared, where deeply penetrating photons can be absorbed in the surface region above the shutter implant. Figure 24 shows the calculated extinction coefficient at -80°C for back-illuminated devices of various thicknesses and a shutter depth of 1.3 ^m. Clearly, a thick device is essential for good extinction out to 1000 nm.

Figure 24. Measured and calculated extinction coefficients. Data and curve for 17-|am-thick device is for T = 20°C, while the 40- and 100-|am calculated extinction is for T = -80°C.

5.2 Hybrid Detectors

Hybrid detector arrays exploit the benefits of a detector structure optimized for optical detection combined with a processing circuit to read out the signal. The detector array is dedicated to detecting the incident photons, while the readout circuit controls the operation and produces a suitable output. Infrared detectors are typically hybrid arrays consisting of a detector array fabricated in the proper material and mated to a multiplexer readout circuit. Hybrid detectors are somewhat more complex to build, but the technology effectively addresses some of the limitations of monolithic sensors, such as low fill factor and process incompatibilities between the detector array and the readout multiplexer. A variety of visible hybrid arrays have been developed with different technologies implemented in the detector array.

5.2.1 Silicon p-i-n Detector Arrays

The p-i-n detector array consists of a thick (~185 ^m) active region of high-purity silicon sandwiched between regions doped p-type and n-type [4]. An example of this type of array is shown in Fig. 25. The illuminated side is implanted n-type, and the side bonded to the readout circuit is doped p-type. A high reverse bias is applied to the device, resulting in a strong electric field that separates the electron-hole pairs created by the photons absorbed in the high-resistivity region. The bulk of the detector array is nearly fully depleted, delivering excellent QE at long wavelengths and good MTF characteristics [22] since the diffusion crosstalk is negligible. The back-illuminated detector array is bump bonded to a CMOS multiplexer with a bump in each pixel. Noise levels comparable to CCD performance are achievable using Fowler's multiple sampling technique.

5.2.2 CCD/CMOS Hybrid FPAs

The CCD/CMOS hybrid FPA combines the imaging qualities of the CCD with the high-speed, low-power, and low-noise capabilities of a dedicated CMOS readout integrated circuit (ROIC). An example of this array is shown in Fig. 26. In a front-illuminated device, the FPA consists of two CMOS ROICs bump bonded to a CCD detector [23]. Each readout circuit is an array of capacitive transimpedance amplifiers (CTIAs) that are connected to each end of the CCD columns with indium bumps. A significant advantage of this configuration is that the fabrication process is simplified since fewer bump connections are required, and the design of the readout electronics is not restricted to the area contained within a pixel, which is the case in a conventional hybrid detector. Without the conventional serial shift register and on-chip output amplifiers, the hybrid CCD operates with much lower power while maintaining excellent imaging performance. The column parallel readout architecture reduces the effective output bandwidth and provides sufficient silicon real estate in the ROIC to implement sophisticated amplifier circuit designs that dramatically reduce the readout noise. The CCD power consumption is also reduced, as a result of the elimination of high-speed serial clocking and high-current output amplifiers. This parallel readout arrangement dramatically improves the total frame rate and significantly reduces the noise floor, since the amplifier bandwidth is considerably lower than the level necessary for a conventional CCD with fewer output ports.

Figure 25. Mosaic array of 2Kx2K PIN hybrid FPAs. Courtesy of Yibin Bai, Rockwell Scientific.

5.2.3 CMOS/CMOS Hybrid FPAs

In CMOS/CMOS hybrid FPAs, a CMOS detector array fabricated for back illumination and biased for deep depletion is combined with a dedicated CMOS readout circuit [24]. A column-wise connection similar to the CCD/CMOS approach described above reduces the number of bump interconnects, lowers power dissipation, and increases speed.

5.2.4 SOI Arrays

Although relatively new, silicon-on-insulator (SOI) arrays show promising prospects. The devices are fabricated with two silicon layers separated by an insulating oxide layer. The readout circuitry is built in the top "device" layer and the photodiode in the bottom "handle" layer. Separate grounding for each layer eliminates substrate bounce and clock coupling. The resistivity of each layer can be tailored for best performance [25].









Figure 26. Prototype CCD/CMOS hybrid FPA. Courtesy of Fairchild Imaging.

5.3 Curved CCDs

It has always been tacitly assumed that image sensors must of necessity be flat, and that optical system designers must therefore take whatever pains and expense necessary to provide a flat image plane. This assumption is no longer valid, and in fact curved CCDs are now a reality, as evidenced by recent work at Sarnoff [26] and Lincoln Laboratory. Figure 27 is a simple demonstration of silicon deformability in which a 20-^m-thick silicon membrane is pressed down on a 175-mm-radius spherical section.

Figure 27. Deformation and buckling of a 20-|am Si membrane over a 175-mm-radius spherical section.

The mechanical limitations on deformability can be estimated from a simple formula. Consider a circular silicon membrane of radius r deformed to a spherical cap of radius R. The maximum strain is at the center of the cap and is given approximately by (r/R)2/6, assuming the silicon thickness is much smaller than r. For a 60-mm CCD (e.g., a 4Kx4K, 15-^m-pixel device) and a 1-meter radius of curvature, the maximum strain is ~6x10-4, which is well below the mechanical limit of ~1% for silicon. The effects of strain on the performance of CCDs have not been thoroughly examined at this point, but preliminary results show the main effect to be an increase in dark current that arises from the decrease in band gap energy Eg. Measurements at Lincoln Laboratory show a dark-current increase that is consistent with a decrease in Eg of 80 meV/(% strain), compared to the theoretical value of 115 meV/(% strain). These numbers can be related to actual dark-current changes using well-known formulas for dark current in silicon [27].

5.4 Orthogonal-Transfer CCD

The orthogonal-transfer CCD (OTCCD) is a unique device in its ability to shift charge in all directions. Figure 28 illustrates a conventional three-phase pixel layout on the left and one of two OTCCD pixel layouts on the right. The unit cell of the OTCCD consists of four phases, and the layout shown here is a symmetrical arrangement of four triangular gates. With the phase-4 gates biased low, phases 1-3 can be clocked to shift charge vertically, while with either phase-1 or phase-3 blocking the remaining phases can shift charge horizontally.

l l Clocked gale l l Clocked gale

Figure 28. (left) Illustration of a conventional three-phase CCD and (right) one of two OTCCD pixel designs.

Conventional three- OTCCD

phase CCD

Figure 28. (left) Illustration of a conventional three-phase CCD and (right) one of two OTCCD pixel designs.

The obvious application of this device in astronomy is to perform electronically the tip-tilt correction to compensate for atmosphere-induced wavefront tilt and telescope shake. Results from a small prototype device (512x512 pixels) were reported at this conference in 1996 [28] and later in more detail [29].

The effectiveness of the device for correcting wavefront tilt is limited to angular distances on the sky of a few milliarcseconds. For wide-field imaging such a device would clearly lose its effectiveness, and a different approach with multiple OTCCDs is needed. Such a device, the orthogonaltransfer array (OTA) [30], is now under development for the Panoramic Survey Telescope and Rapid Response System (Pan-STARRS) program. Figure 29 illustrates the basic elements of the OTA under development. The device consists of an 8x8 array of OTCCDs or cells, each comprising about 500x500 pixels. The parallel clocks and the readout amplifier are under the control of a small block of NMOS logic that enables each cell to be controlled and read out independently. In this way each cell can be clocked in a manner that is optimum for the local image motion. Prototype devices have been demonstrated, and the first test results are described elsewhere in these proceedings [31].

Figure 29. Principal elements of the OTA: (left) overall chip layout comprising an 8x8 array of OTCCD cells, (center) OTA cell with control logic, and (right) one of the OTCCD geometries.

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