Emerging Technologies

For monolithic active pixel architectures the pixel area must be shared between the photodiode and the access and amplification transistors, as seen in the plan view and schematic cross-sectional view of Fig. 16. The photocollection junction is typically formed at the drain-substrate or well-substrate interface. It is clearly seen in these views not only that the fill factor of the pixel is less than 100% but also that the fabrication of the photojunction and access transistors must be co-optimized, with some necessary compromises on layout density, absorption layer thickness, and device isolation. Foundries targeting consumer applications typically apply microlenses to compensate for the loss of optical fill factor.

Figure 15. CMOS pixel process flow: (a) deposit oxide and spin coat organic material, (b) etch back and remove oxide, (c) remove organic material and pattern oxide (photo/etch), and (d) form silicide on peripheral devices. Adapted from Wuu et al. [8].

6.1 Vertically Integrated Active Pixel Imager

Without further limiting the pixel fill factor, monolithic architectures also require that addressing and signal processing circuitry be placed at the periphery of the array. In contrast, a three-dimensionally (3-D) stacked circuit construct, such as shown in Fig. 17, relieves many of the limitations inherent to monolithic structures. Active-pixel focal plane architectures are well suited for 3-D interconnection because signal integration, amplification, and readout can be in close proximity to the photodetection elements while still achieving 100% optical fill factor. The further capability to perform complex signal processing behind every pixel can dramatically reduce total image sensor power and bandwidth requirements.

Figure 16. Example of three-transistor pixel layout (a) in plan view and (b) in cross-section.
Figure 17. Advantages of vertical integration: (left) conventional monolithic APS compared with (right) 3-D pixel.

Vertically hybridized flip-chip imagers already offer independently optimized photodetector and readout multiplexer designs that can achieve scientific-grade image sensor performance [9]. However, these bump-bonded approaches are limited to two circuit layers, to large pixel sizes (>18 ^m), and do not permit post-integration hydrogen-passivation anneals, which are critical for dark current suppression. In Fig. 18 a feature-size comparison is made among three methods to vertically interconnect circuit layers: (a) bump bond, (b) insulated through-silicon vias, and (c) Lincoln Laboratory's SOI based via. The Lincoln integration method is extendable to three or more circuit layers and is capable of achieving far smaller pixel sizes than possible with bump bonding.

The process technology for the method in Fig. 18(c) has recently been used to demonstrate a four-side abuttable 3-D integrated 1024^1024, 8-|m pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-|m-square 3-D vias in every pixel. The 150-mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-|m gate length fully depleted (FD) SOI CMOS readout circuit layer [10].

10 um

Figure 18. Approaches to 3-D integration: (a) Bump bond used to flip-chip interconnect two circuit layers, (b) two-layer stack with insulated vias through thinned bulk Si, and (c) two-layer stack using Lincoln Laboratory's SOI-based vias. Illustrations are to scale. Photo in (b) courtesy of RTI.

A cross-sectional scanning electron micrograph (SEM) through several 8-|m pixels of a functional active pixel imager is shown in Fig. 19. The oxide-oxide bond between the two tiers is imperceptible. A 3-D via connects tier-2 FDSOI CMOS metal 3 to tier-1 (diode) metal 1, and a metal cap (back metal 1) covers the 3-D via plug. The 50-nm-thick SOI transistor features can be seen near the top of the SEM. The dominant misalignment (~1 ^m) is created by the wafer-to-wafer bonding step; newer tools and methods in development are expected to further reduce this misalignment.

Each sensor contained over 3.8 million transistors and over one million 3-D vias. We measured pixel operability in excess of 99.9% with the principal yield detractor arising from column or row dropouts, i.e., not 3-D vias. The devices have successfully been processed through diode wafer thinning for back-illumination operation.

Figure 19. Cross sections through 3-D imager.

The high degree of pixel functionality can be seen in Fig. 20, which presents an image acquired by projecting a 35-mm slide onto either front-illuminated or back-illuminated processed imaging devices (different chips).

6.2 Digital focal plane architectures

Conventional analog focal plane architectures reach a readout bottleneck when the system implementation demands wide-area coverage, high frame rates, and high bit precision. By digitizing the signal while the photoelectrons are being collected, rather than after charge accumulation, the need for large charge storage capacitors and highly linear analog electronics can be eliminated. Additionally, the power dissipation and noise problems, which result from communicating analog signals across an imager at high data rates, are greatly reduced.

Using hybridization methods, Lincoln Laboratory has demonstrated 32*32-pixel focal planes based on Geiger-mode avalanche photodiodes (APDs), which can detect a single photon and produce a digital logic pulse directly from the detector [11]. As shown in Fig. 21, the detector is connected directly to a CMOS inverter, the output of which serves as a stop signal to a digital timing circuit, or in the case of intensity imaging as an increment signal to a counter. This digital-domain design yields power savings, noiseless readout, and quantum-limited sensitivity. Multiple operating voltages for arming the APD and operating the low-power digital circuitry can be readily accommodated. By using the SOI-based, oxide-bonded, micron-scale 3-D interconnection technology previously described, the pixel pitch of the array can be further reduced and the timing resolution improved, to produce a scalable architecture.

Figure 20. Four-side abuttable vertically integrated imaging tile: (left) front illuminated and (right) back illuminated (partial frame of top 700 rows).

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