Hybrid Cmos Technology

The hybrid CMOS revolution began in the mid 1970s when the indium bump interconnect technology was invented. By 1990, CMOS processing of silicon was standard for the commercial analog and digital integrated circuit industry. The CMOS process has continuously improved because of demands of the computer industry, allowing higher-density circuits and large array formats. At the same time, indium bump hybridization has also improved to the point where 16 million pixels per array can be reliably connected.

The hybrid CMOS approach separates the problems of (1) converting electromagnetic radiation into an electronic signal and (2) amplifying the electronic signal, processing it, and multiplexing the signals from many detector elements onto a single output line. In a hybrid CMOS device, the first function is performed by a detector array that is typically electrically connected to a CMOS integrated circuit chip using an array of indium bumps, one per detector element. The CMOS chip, often called a ROIC (readout integrated circuit), performs the second function. A detector hybridized to a CMOS ROIC may be called a hybrid array, a sensor chip assembly (SCA), or a focal plane (FPA).

Because the detection and electronics functions are separated in a hybrid CMOS SCA, the design and processing of detectors and ROICs can each be optimized for its own function. In addition, detectors and ROICs can often be interchanged, that is, a given ROIC design might be hybridized to different detector arrays depending on the wavelength of interest. Similarly, a given detector array might be hybridized to different ROICs depending on the desired frame rate, well capacity, or other signal processing functions.

Wavelength (nm)

Figure 8. Spectral QE of a monolithic CMOS image sensor with three transistors per pixel.

Wavelength (nm)

Figure 8. Spectral QE of a monolithic CMOS image sensor with three transistors per pixel.

4.1 Detectors

Some of the detector materials available in large array formats and compatible with the CMOS hybrid approach are shown in Table 1. The spectral range of each material is listed along with the approximate operating temperature to achieve much less than 1 -electron/second dark current. All of these detector materials have been demonstrated in formats of 1K x 1K or greater, all have essentially 100% fill factor, and all have very nearly 100% internal QE if the detector is properly designed and fabricated. All of these detectors, with the exception of Si:As, are generally produced as p-on-n diode structures and are interchangeable with regard to ROIC hybridization.

Table 1. Detector Materials Available for Large-Format CMOS Hybrids (SCAs).

Spectral

Operating

Detector

Range(a)

Temperature(b)

Material

(|am)

(K)

Si PIN

0.4-1.0

~200

InGaAs(c)

0.9(d)-1.7

~130

HgCdTe(c)

0.9(d)-1.7

1.7 |am

~140

2.5 |am

0.9(d)-2.5

~90

5.2 |am

0.9(d)-5.2

~50

10.0 |am

5.0-10.0

~25

InSb

0.4-5.2

~35

Si:As IBC (BIB)

5.0-28.0

~7

(a) Long wave cutoff is defined as 50% QE point.

(b) Approximate detector temperatures for dark currents <<1 electron/second.

(c) Requires special packaging due to thermal contraction mismatch between detector and ROIC.

(d) Spectral range can be extended into visible range by removing substrate.

(a) Long wave cutoff is defined as 50% QE point.

(b) Approximate detector temperatures for dark currents <<1 electron/second.

(c) Requires special packaging due to thermal contraction mismatch between detector and ROIC.

(d) Spectral range can be extended into visible range by removing substrate.

One of the design issues facing the hybrid CMOS structure has been how to deal with differences in thermal contraction of the detector and ROIC as the SCA is cooled. For example, if the detector contracts much more than the ROIC, the indium bump connections could be torn apart upon cooling. The problem becomes more severe for larger arrays and for lower operating temperatures. Fortunately, for a thinned detector such as InSb, the membrane-like detector (10 ^m thick) is able to stretch to match the contraction of the ROIC. For thick detectors, such as HgCdTe and InGaAs, detector manufacturers have devised mechanical structures to force the ROIC to contract the same amount as the detector material, thus nearly eliminating stress at the indium bump interface. For silicon-based detectors, such as Si PIN and Si:As, there is little differential contraction compared to a silicon CMOS ROIC, and thermal cycle reliability is not a concern.

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