Info

DAQ- PC

Figure 5. Configuration of a cPCI based DAQ-system for a fast CCD readout, comprising up to eight readout nodes. The configuration allows the operation of a 264x264 CCD at 1100 frames/sec, generating a constant data flow of 140 MB/sec.

To apply a threshold setting in the detector data, the data must be corrected for offset, gain and common-mode variations. As long as the data flow does not exceed the PCI-bus speed, data reduction could be done online by software. But for a high-speed detector setup, hardware data reduction is needed. The offset-, gain-, common-mode-corrections and the data reduction by threshold settings for both ADCs per ADC unit is done with a fast FPGA processor, equipped with a large, high-speed computer memory. The performance of the FPGA data processor also allows advanced computations of the data, e.g. cluster analysis. In the case of the CCD system in a Shack-Hartmann wavefront sensor, a centroid determination, including the determination of intensity and sigma of the distribution, of all dedicated sub-images will be performed with very short latency times. The software realization of this feature is under development.

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