The measurement of the Quantum Efficiency (QE) of CMOS hybrid arrays recently produced implausible efficiencies exceeding 100%. Many factors such as radiation geometry, blackbody calibration, temperature

dependence of the filter transmission, and filter leaks may contribute to this problem [1]. During the characterization of infrared arrays, we have tried to reduce the errors of each factors listed above without succeeding in obtaining a quantum efficiency in K-band of a ^c=2.5^m HgCdTe Hawaii-2RG array below 105%.

The remaining major uncertainty in our QE measurements was the conversion gain, C0/e, measured in units of electrons per millivolt. The nodal capacitance C0, which is the capacitance of the integrating node, is composed of the voltage dependent diode capacitance of the detector pixel and the fixed gate capacitance of the unit cell source follower gate. The nodal capacitance of CMOS hybrids has, until now, usually been determined by the widely used shot noise method that assumes photon shot noise limited performance of the detector. Photons are governed by Bose-Einstein statistics. If the photon energy is small compared to kT (k is the Boltzmann constant and T is the absolute temperature of the radiation source), the variance of the integrated number of photons is equal to the mean number of photons. In this case, the nodal capacitance C0 can be calculated from the slope of the plot of noise squared signal versus mean signal according to Eq. (1). However, this equation only holds true if the signals of neighboring pixels are uncorrelated as explained in Sec. 3.

To obtain the nodal capacitance C0 by a direct measurement that does not rely on statistical methods, a simple technique has been developed. This technique compares the voltage change of a large calibrated external capacitor to that of the unknown nodal capacitance C0, which is many orders of magnitudes smaller.

During normal operation the reset voltage, Vreset, is connected to an external bias voltage of the detector control electronics and the bias provides the charge required to reset the integrating node capacitor. The hardware setup for the capacitance comparison simply entails adding a switch (relay) between the bias and Vreset and adding a calibrated capacitor, Cext, between Vreset and detector substrate voltage Dsub as shown in Fig. 1. The external capacitor is charged to the nominal reset voltage and disconnected (using the relay) from the external bias. The charge to reset the nodal capacitor C0 of

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