Introduction To L3 Technology

Conventional CCDs are limited by the intrinsic read noise of their output FET transistors in many applications. Reducing the noise bandwidth by slowing the readout is generally the only option if the system is read-noise limited. The engineer is then forced to make a compromise between speed and noise. L3 technology allows these two factors to be decoupled: making megahertz pixel rates possible with sub-electron read noise. This is achieved by the addition of a multi-stage avalanche gain register between the serial register and output transistor. Photo-electrons traversing this register during serial transfer emerge into the output node as a substantial charge packet that induces a voltage signal far in excess of the amplifier noise. The actual gain level can be tuned from unity up to >103 by varying the amplitude of the multiplication clock phase in the gain register. Clock amplitudes are typically 40-45V, larger than those available in most controllers, although still easily generated using custom clock generator boards based around

readily available DC:DC converters. e2v technologies [1] have, thus far, applied L3 architecture (see Fig. 1) to a number of small CCDs, although in principle it can be added to any chip design format.

The multiplication register can be thought of as the solid state analogue of a photomultiplier tube with a very low dynode gain of around 1%. For this reason the gain register contains 520 stages. This low probability of multiplication has the unfortunate side effect of introducing an additional statistical noise source that degrades the SNR by a factor of V2. The effect at lower signal levels is more than compensated for by a lack of read noise. Overall, the multiplication noise has the same mathematical effect as halving detector quantum efficiency (QE). L3 technology is valuable in certain read-noise limited, low flux niches, namely wavefront sensing and rapid spectroscopy. It is not a panacea, and in higher-flux applications a conventional CCD may still be the best choice.

Figure 1. L3 CCD schematic.

All CCDs exhibit clock induced or 'spurious' charge (CIC); fast clock edges generate high electric fields that produce stray electrons within the silicon. If generated by the parallel clocks, these electrons are indistinguishable from photo-electrons and may be mistaken for dark current. If generated by the serial clocks they may be mistaken for increased amplifier read noise. The effect is small and may only be revealed in heavily binned images. For example, a poorly prepared CCD4280 had an observed read noise that increased approximately as the square root of the horizontal binning factor. Dropping serial clock amplitudes by a couple of volts eliminated the problem. For L3 CCDs a CIC of a fraction of an electron can limit the performance. Indeed, all L3 CCDs tested thus far have been CIC noise limited. Minimising CIC requires special attention to the clock edges and a minimisation of the on-time of the multiplication clock. If this is done carefully then approximately one pixel in 1000 contains a spurious electron.

Due to controller limitations we have been forced to use slower pixel rates and 1 pixel in 10 has been a more typical result.

It may seem remarkable to be able to measure such low levels of CIC. However, in an L3 image single electron events clearly stand out as discrete 'spikes'. The windowed frame in Fig. 2. shows the image area, serial overscan and parallel overscan of a CCD97 L3 CCD. The single electron events are obvious. Notice that there is a spread in brightness of the events. This is a consequence of multiplication noise. Also noteworthy is the relative absence of events in the broad overscan regions at the top and right of the image. These regions contain pixels that do not originate in the image area of the CCD (which is a frame transfer device) indicating that the image area clocks were still in need of some fine-tuning. Underlying the image is a faint Gaussian background with a hint of pattern noise, all well below the single electron event level.

Figure 2. Windowed bias frame from an L3 CCD.

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