Leakage Current

The leakage current measurement typically involves applying a fixed voltage across two groups of detector pins (e.g. serial clock phase 1 at +15 volts and substrate at zero volts) and then recording the resulting DC current flow. While the test is quite simple to perform, it yields invaluable information regarding the health of the detector if the current resolution is sufficiently high. For example, the typical leakage current into the reset gate on most CCD detectors is approximately 5 nA, and most of this is frequently due to parasitic loads. If the leakage current were to rise to 100 nA, say as a result of an ESD event occurring during a critical packaging step, the detector would most likely continue to function within specification. However, the rise in leakage current is a likely indicator of a fatigued gate which could potentially result in an early-life failure. Electro-Optical testing typically does not discover such fatigue and, hence, the detector would continue to be treated as a flight candidate. It is therefore recommended that leakage current testing be performed after each significant handling step in the FPA assembly process.

Using an automated DC test system, with a programmable matrix and precision voltage/current sources, several hundred leakage current tests can be performed in a matter of minutes and the results can be easily tracked over time. As an added precaution during testing, each stimulus source connected to the CCD should have compliance limiting capability. That is, every voltage source should have a programmable current compliance limit, as should every current source. Most modern Semiconductor DC Parameter Analyzers and Programmable Stimulus Measurement Units incorporate compliance limiting and, hence, using such instrumentation is highly recommended during all types of DC testing.

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