Measurement Results

Proving the low noise capabilities of the CRIC II chip was one of the main testing goals. Figure 5 shows 1.9 ADU rms noise that was measured running the chip at -110°C and at 100K samples per second. This translates to about 6.5 ^V rms noise, or slightly less than two electrons. The warm performance is slightly worse due to higher thermal noise. At room temperature, we measured 2.3 ADU or 8.3 ^.V rms noise. All noise measurements were done using the highest integrator gain. For larger signals at lower integrator gains, the noise is no longer dominated by the input stage, but by the A/D converter. For signals greater than 4K electrons, we measured 0.8 ADU or 12.8 electrons rms noise. For signals above 64K electrons we measured 0.9 ADU or 28.8 electrons rms noise, both very close to the quantization noise plotted in Fig. 3.

A/D Counts

Figure 5. Noise histogram from 10000 samples at -110°C.

A/D Counts

Figure 5. Noise histogram from 10000 samples at -110°C.

The linearity of a pipeline A/D converter is very good by design. Figure 6 shows 1 ADU rms nonlinearity for a signal that varies over the full scale of the middle slope of the multi-slope integrator.

The power consumption of the system is 17 mW/channel at 100 KHz. The power draw is roughly equally distributed among the analog input stage and the pipeline A/D. Our CCDs typically dissipate just as much power in the source follower load.

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