The performance and functionality of the SIDECAR ASIC have been examined at room temperature  and at cryogenic temperatures down to 37 K. Room temperature performance is important for applications that operate detectors at or near room temperature (visible light and/or high background) as well as for convenient testing and verification of the ASIC itself. Whereas cryogenic performance is essential for low background detector systems that benefit from analog to digital conversion close to the FPA.
The test results will be presented in the following two sections. Sec. 3.1 describes the performance of individual ASIC components such as ADCs and preamplifiers. In Sec. 3.2 measurement results from a complete system test comprising the SIDECAR ASIC and the HAWAII-2RG will be discussed. Both types of results have been obtained using a PC-based environment with a custom-built test board. Room temperature tests have been carried out at Rockwell Scientific; cryogenic tests have been performed at the Institute for Astronomy in Hilo, Hawaii.
The purpose of the first set of tests included the verification of the correct functionality and the measurement of the analog performance of all integrated building blocks. As part of these initial tests, the test environment had to be completed and various ASIC micro-code programs had to be written. Aside from a leakage problem in one of the integrated memory modules, all digital and analog components were fully functional. Subsequently, fabrication of a second ASIC revision has completely solved the problem in the memory module. The following paragraph lists all building blocks that have been measured and verified:
• Serial/parallel data interface to and from SIDECAR
• Micro-controller plus program & data memories
• Timer/Counter modules
• Digital I/O block for clock generation
• Array processor for parallel data processing
• Analog bias generator for internal/external voltage & current biases
• Integrated 2.5 V voltage regulator for digital supply voltage
• 12-bit ADC, DNL < ± 0.3 LSB, INL < ± 0.8 LSB, noise < 0.4 LSB
• 16-bit ADC, DNL < ± 0.4 LSB, INL < ± 2.3 LSB, noise < 3 LSB
• Preamplifiers, noise at T=300K: 20^V, noise at T=40K: 12 ^V
The analog performance of the two types of on-chip ADCs has been examined with respect to linearity and noise. In the case of the 12-bit ADC, the Differential and Integral Non-Linearities (DNL and INL) at a sample rate of 7.5 MHz are shown in Fig. 3. At room temperature and at T=40K, the 12-bit ADCs exhibit excellent DNL and INL as well as low temporal noise of less than 0.4 LSB. No significant difference in performance has been observed for sampling rates of 10 MHz.
Likewise, the 16-bit ADC shows good performance with respect to DNL and INL (see Fig. 4). In terms of noise, a compromise between the noise level and the power consumption suitable for JWST was required. At a power level of 1.3 mW and a sampling rate of 100 kHz, the ADC noise is 5 LSB at room temperature and 2.5 LSB at T=40K. This performance fulfills JWST requirements with margin. The noise can be reduced by increasing the ADC bias current at the cost of higher power consumption. However, no measurements at higher bias conditions have been undertaken.
The preamplifier provides control over the analog signal gain and the analog signal bandwidth by means of programmable capacitors and resistors. Its performance has been evaluated under JWST conditions for 100 kHz pixel rate, using a bandwidth of 300 kHz and a gain of 27 dB. The measured noise is 20^V (input-referred) at room temperature and less than 12^V at 40K. This combines the noise of the preamplifier and the noise of the 16-bit ADC results in a total analog noise of 18^V for cryogenic operation. As mentioned above for the ADC, increasing the bias current (power consumption) can further reduce the amplifier noise.
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