We are very pleased with the performance of the CRIC II chip. The third generation chip is in design. This will incorporate internal time sequencing and a 14-bit A/D with auto calibration. This will greatly simplify the interface and pinout of the chip. We also continue to develop a second ASIC that contains DC bias voltage DACs, timing generation and clock line drivers.

Figure 6. The integral nonlinearity is shown as the deviation from a line fit as a function of the injected charge.

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