The basic process by which scientific CCDs are manufactured is essentially the same as it was 30 years ago. This process for a three-phase device, depicted in Fig. 3 together with a scanning electron micrograph (SEM) of a fabricated device, is based on the use of doped polycrystalline silicon, or polysilicon, films for the gate material. Beginning with a substrate wafer, a thin gate dielectric layer(s) is grown on the surface, and a layer of polysilicon is deposited and lithographically defined to produce the first set of gates corresponding to one clocked phase. The wafers are then placed in a thermal oxidation furnace where the thin SiO2 layer is grown over the polysilicon. For processes that employ a Si3N4 layer as part of the gate dielectric this oxidation step leaves the exposed dielectric unchanged, since Si3N4 is a barrier to O2 and H2O, and prevents the SiO2 beneath it from becoming thicker. This is an advantage from the point of view of leaving the threshold voltages, and thus the clock drive voltages, the same for all three phases. For the second and third phases the process is repeated twice, but in each case the gates must slightly overlap the adjacent gates to ensure good control of the electrical potential in the CCD channel below.
2.3 CCD vs CMOS: Process Comparisons
As CMOS sensors begin to attract more attention, it is worthwhile comparing various aspects of the two technologies. Here, we examine the device processing differences, while later in Section 4 performance is compared.
To understand scientific CCD wafer processing, it is worth noting that for pixel sizes of interest in astronomy (~10-20 |m) the gate features have dimensions of several |m. In comparison to state-of-the-art silicon IC technology, where feature sizes of <0.1 |m are now the norm, these are extremely large geometries. On the other hand, CMOS sensors must have several field-effect transistors and other components placed inside the pixel, along with metal lines, to address, reset, and read out the pixel. This high component density requires the tight sub-^m lithography characteristic of current CMOS wafer fabrication.
The simplicity of the CCD pixel and its readout circuit and its relatively generous design rules enable CCDs to be manufactured with fewer photomasks (typically 10-15) than CMOS (15-30 photomasks) and with less sophisticated (one might say "lagging edge") technology. In addition, CCDs have for the most part kept the relatively thick gate dielectrics (50-100 nm) and polysilicon oxide thicknesses (100-300 nm) from decades ago. By contrast, CMOS processes use gate dielectric thicknesses of the order of 5 nm or less. This, of course, has implications for device yields, since particulates of a size that may produce a fatal short in the gate oxide of a CMOS device may hardly affect a CCD. This fact, combined with the superb cleanliness and extremely low levels of contaminants in the process chemistry of modern wafer fabrication, have enabled high yields for the huge CCD die sizes alluded to in the introduction.
An important distinction between CCD and CMOS fabrication lies in the material requirements. CMOS requires thin epitaxial layers grown on heavily doped (low resistivity) substrates for proper circuit performance, whereas CCDs can be fabricated on almost any substrate, including the highly desirable high-resistivity material needed for deep-depletion depths. Conventional CMOS imagers, therefore, are fundamentally limited to extremely poor near-infrared response. For this reason the only inroads that CMOS can make into the astronomy market will be by hybrid devices, described in Section 5.2.1, in which a separate diode array, made on high-resistivity silicon, is bump bonded to a CMOS readout multiplexer (MUX) . Whether this can be done in a cost-effective way remains to be seen.
CMOS has always appeared attractive for integrating on chip all of the support functions needed to drive a sensor, such as clock waveform timing and generation, biases, video processing, and analog-to-digital conversion. It is possible, and in fact has been demonstrated, that a CMOS process can be integrated into a CCD process, but the complications involved are significant and can involve performance compromises and extra costs. A more promising route is to combine CCD and CMOS, either as a bump-bonded hybrid or using newer approaches involving direct wafer bonding , to obtain an integrated device with all the support features in one compact sensor. Even a somewhat less integrated approach in which CCD and CMOS reside close to each other in a shared package is attractive in reducing the huge volume and power of the electronics needed to drive the coming generation of Gpixel focal planes. Custom CMOS, unconstrained by CCD process requirements, is now relatively inexpensive compared to large scientific CCDs, so that the case for hybridization is very compelling. Examples of this approach are described in Section 5.
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