Sidecar Architecture

The SIDECAR ASIC represents a fully programmable control and digitization system for analog image sensors. It is designed to operate at room temperature as well as at cryogenic temperatures down to 30 K. The architecture can be divided into the following major blocks, which are shown in Fig. 1: analog bias generator, A/D converter, digital control and timing generation, data memory and processing, and digital data interface.

Figure 1. Block diagram of the SIDECAR ASIC.

The analog bias generator consists of 20 independent channels, each of which is composed of a 10-bit digital-to-analog converter and an output buffer with adjustable driver strength. They are basically programmable current and voltage sources. For reading out the analog detector signals, the SIDECAR provides 36 analog input channels. Each channel can be digitized by on-chip ADCs offering 16-bit resolution at sample rates up to 500 kHz and 12-bit resolution at sample rates up to 10 MHz. A fully programmable and application optimized micro-controller is responsible for overall ASIC control and for generating specific timing patterns of the image sensor clocks. A total of 32 digital I/O channels can be individually adjusted for driver strength and signal direction. Additional on-chip memory permits simple data processing functions like pixel averaging or data sorting. Finally, a serial and a parallel data interface are implemented to read the digitized pixel values and to program the ASIC.

The primary driver for this controller-on-a-chip approach was the development of the James Webb Space Telescope (JWST), successor to the Hubble Space Telescope. Requiring 16-bit accuracy at a temperature of 37 K without active cooling, the JWST put stringent requirements on the performance and power consumption of the ASIC. The JWST goal is 16-bit conversion on 4 parallel channels at a power consumption of less than 10 mW, including bias generation, clock generation and data transmission. As the next section on measurement results describes, this goal has been achieved, and the SIDECAR ASIC is fully suitable for JWST and other space-based applications, in addition to ground-based applications.

Figure 2 shows a micrograph of the SIDECAR chip as well as a packaged ASIC in a 337-pin ^PGA package. A summary of the important properties is given in Table 1.

Figure 2. (left) Micrograph and (right) packaged SIDECAR ASIC.
Table 1. Summary of the SIDECAR ASIC properties.

Die Dimension

22x14.5 mm2


0.25 ^m CMOS

Analog Input

36 independent channels, fully differential


Programmable gain (-3 to 27 dB) and bandwidth

16 bit ADCs

(1 mW / channel at 100 kHz). Up to 500 kHz sample rate

12 bit ADCs

(10 mW / channel at 5 MHz). Up to 10 MHz sample rate

Bias Outputs

20 output channels, selectable voltage or current DACs

Digital I/O

32 channels, fully programmable


16 bit RISC, low power, excellent arithmetic capabilities

Program Memory

16 kwords (16 bit / word)

Data Memory (^C)

8 kwords (16 bit / word)

Data Memory (ADC)

36 kwords (24 bit / word)


Adding & multiplying and DMA control per ADC channel

Digital Interface

LVDS or CMOS, custom serial protocol, up to 32 lines

Operating Temperature Range

30 K - 300 K


Complete design is single event upset protected

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