Siliconus maximus

Richard Bredthauer1 and Michael Lesser2

1Semiconductor Technology Associates, Inc., 2Steward Observatory, University of Arizona

Abstract: Recent discoveries reveal new promise for a technology formerly assumed to be extinct, CCDs. Silicon processing technology has made tremendous strides over the past 30 years enabling higher quality and ever larger CCDs. We will discuss prior and ongoing experience with large area CCD focal-plane arrays, which include innovative design andfabrication techniques that ensure performance and yield. Semiconductor Technology Associates (STA) will describe the development of an ultrahigh resolution large area CCD (up to the maximum limit of a 150 mm wafer) integrating high dynamic range and fast readout.

Key words: Ultrahigh resolution CCD, 4K*4K imager, VLSI.


This paper summarizes rapid progress made in the past few years in the development of large area scientific imaging arrays. CCD imaging arrays from 3cmx3cm (2048x2048 pixels) to 9cmx9cm (10Kx10K pixels) will be described. These devices show exciting promise in a variety of space-based, astronomical, and high resolution commercial imaging applications.

Bipolar transistors were fabricated on 1.5" silicon wafers in production during the late 60's. By the early 70's a stable MOS process had been established and wafers became 2" and 3" in diameter. Boyle and Smith of Bell Laboratories described and demonstrated working Charge Coupled Devices in 1970 [1,2]. They are elegantly simple devices which manipulate signals as small packets of charge from one area to another across the silicon surface. An array of MOS capacitors is fabricated over the silicon. The

discrete packets of charge are coupled from one capacitor to the next by alternately clocking voltages from one capacitor gate to the next. For scientific applications the signal packets are as small as only a few electrons. During the 70's the quality of the silicon starting material, process chemicals and laboratory cleanliness had not matured adequately to fabricate devices larger than several millimeters on a side. Imaging arrays of 380^488 pixels demonstrated good, high level performance, but showed significant signal trapping and fixed pattern noise at signal levels less than 1000 electrons. CCDs were proposed to fulfill a variety of functions ranging from analog memories, adaptive filters, radar signal processors, and imaging devices. The mainstream of silicon processing proceeded rapidly pushing the technology in digital CMOS and DRAMS.

Production wafers moved from 3" to 4" to 5" to 6" to 8". Presently Intel, Samsung and other major facilities are now utilizing 12" wafers for production. The cost of such facilities is several billion dollars and can only be sustained by very high volumes. Digital devices have taken over the potential CCD applications of signal processing and memory. Despite these changes CCDs still remain the dominant choice for very high end/resolution imaging applications.

Arrays as large as 4 centimeters on a side (4096^4096 pixels) were demonstrated in the late 80's [3]. Those imagers were designed with a pixel size of 15 ^m sq. fitting a 4" (100mm) wafer (see Fig. 1). CCDs have one of the largest active gate areas of any semiconductor device. Creating a design which is tolerant to predominant process defects is key to yields.

Figure l. 4K*4K on a 4" wafer.

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