The FPGA design consists of a state-machine that fully encompasses the clocking sequences required to read out a full frame, a sub-frame or clear the CCD. The frame "readout" or "clear" is triggered by a single "start" strobe. Three on-chip RAM memories hold the clock patterns, the iteration numbers for the various patterns and the clock rate to use for a given pattern. A GUI was developed for the Windows platform to easily create the RAM memory map file to control the circuit, set the biases on the DACs and program the AD9814 CCD processor. The state-machine is sufficiently flexible that for most applications, the user will not need to modify the FPGA circuit or the FX2 microcontroller code. In other words, the user is shielded from the low-level details of the system
It is anticipated that the first version of the camera will be operational before the end of 2005. This initial version will use the Texas Instruments TC253SPD sensor. Future enhancements may include a "slow-scan" version of the video board which would use a 16-bit CCD signal processor to operate conventional, low-noise CCDs, at slower data rates.
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