The chip has been working correctly for almost 3 years at 77K. However, the results presented in this section were obtained at 115K, the temperature of the Printed Circuit Board (PCB) containing the chips. Tests will be repeated in the future for a PCB temperature of 77K (that is not necessarily the chip's internal temperature, whose value is unapparent).
The circuit in Fig. 3 allows us to obtain the input noise density of the amplifier. The offsets are used to guarantee that the output is within range. The noise at the output is basically due to the input noise of the first amplifier. The noise due to the remainder of the amplifiers and to the offsets is negligible in this circuit.
QPA35Q- FAN OUT OPA627 - PREAMP
Vdet (Detector output )
Vdet (Detector output )
Gala 1 in controller. A/D Jigndi between 0 and
Figure 3. Circuit used for obtaining the amplifier input noise density.
The total amplification is so high (~68000) that even a low resolution digitizer such as a digital oscilloscope is enough to obtain the data. The noise density is obtained by calculating a Fourier transform of the data. Sharing the total gain among several amplifiers allow us to keep the system bandwidth at a relatively high value. By doing so the noise density can be calculated at frequencies of at least 100 kHz in order to ensure that it is white noise.
The main result is that the noise variations are small. When cold, there seems to be a very slight increase in the 1/f noise of the amplifier and a decrease (around 25%) in the white noise.
The nominal bias current at room temperature is so low (0.5 pA) that no tests were carried out in cryogenics. Although there could be small changes, they are not expected to vary the bias current in an appreciable way, in the sense that it will be kept in the range of a few pA or less.
As for the offset voltage, in this chip it depends appreciably both on the common mode voltage at the inputs of the amplifier and the temperature. Even though there is a clear dependence of the offset on temperature, the maximum voltage offset observed at the input is kept at a similar value (700 ^V at 115K versus 500 ^V at room temperature). In the future, tests must be performed to determine if the offset drift with temperature is similar under the chip nominal temperatures and in cryogenics.
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