The Panstarrs Controller

The controller we are developing for Pan-STARRS must be very fast, high density, and low power. This is an ideal application for one or more ASICs, but in our judgment ASICs do not yet have the maturity to field a system in the next few years. We have therefore elected to build a new controller around the best discrete parts we can presently find. Our goal is to meet the performance requirements while trying maintain simplicity and low cost. Our basic controller, illustrated in Fig. 5, is a PC board which is 3 U wide and about 16 cm long. It dissipates about 15 watts.

Figure 4. A solid body rendering of the Pan-STARRS Giga-pixel Camera, complete with L3 cryostat window and 8 controller boxes.
Figure 5. This figure illustrates schematically how 2 OTAs (16 channels) are connected to a preamp board and a DAQ3U board, and how these are interfaced to a generic pixelserver running Linux.

This "DAQ3U" board has an FPGA for communications, clock and bias generation, signal chain operation, and arithmetic operation on digital samples. One design requirement that makes our controller unique is the need for independent control of the OT readout and correction for each OTA. This requires a design that is easy to program and communicate with, and the FPGA selected has an integral hardcore CPU.

A 16 channel preamplifier/buffer board is paired with its corresponding DAQ3U board to run 2 OTAs. Two of these board pairs are assembled to run a row of 4 OTAs. Two sets of these pairs are placed into individual subchassis to run 8 OTAs. The sub-chassis are assembled 4 wide into a frame that sits on either side of the cryostat. This frame is exactly the same width as the two rows of OTAs being served, so that the detector/controller combination can be extended indefinitely.

The DAQ3U board also hosts 1 Gbit ethernet fast enough to read out and deliver data in real time to a pixelserver host computer, which can use a conventional ethernet interface card. We use standard internet protocols for communications. We also provide 256 Mbyte of on-board ECC memory (standard commercial laptop memory), which enables us to read two entire OTAs (50 Mpixels) and begin another exposure before dumping the data to the pixelserver. Although the Gbit ethernet bandwidth is adequate to read out an OTA within 3 seconds, we would be vulnerable to latencies on the pixelserver. We can imagine modes in which the need to dump more than 16 bits per pixel may arise. It therefore seems prudent to provide on-board memory to maximize flexibility and robustness.

The DAQ3U is implemented as a 14 layer printed circuit board with 50 ohm controlled trace impedance and matched length on critical digital and analog traces. Multiple ground planes are also employed for noise shielding. Version 2 of this board will be split into a mother/daughter board configuration that splits digital and analog functions, and increases the channel density from 12 to 16. The PCB has multiple fine pitch (1 mm) ball grid array components with as many as 896 balls per device. We have also paid attention to the lengths and impedances of the lines on the rigidflex board which connect the OTAs to the controllers.

The preamplifier design is extremely simple to save space. Each channel amplifies, provides a DAC based offset voltage and filters the video output. There are no dual slope integrator or clamp and sample circuits. We have tried both DC and AC coupling the OTA outputs into the preamps, and are presently getting better performance with AC coupling because it is easier to take out the cell-to-cell offsets. Analog voltage levels are provided via Analog Devices AD5532 DACs (32 outputs at 14 bit resolution) current buffered by separate driver ICs. Note that we also have to provide relatively unusual, large negative biases of about -40V for the detector substrate bias.

A full 64 OTA mosaic will have 512 video outputs requiring very fast, high density ADCs. We selected the Analog Devices AD9826 which offer three channels of 16 bit A/D and CDS, at speeds up to 12 MHz for a single channel and 5 MHz for all three channels simultaneously. We have done extensive testing of the AD9826 by building a daughter board, which replaces the Datel 937 ADC used on an SDSU video board, leaving the other channel alone for comparison. Our experiments indicated that the AD9826 is as linear and accurate as the Datel A/D. The AD9826 has no problems with sampling a single channel at 10 MHz, but the AD9826 has 3 ADU of noise. This noise appears to be uncorrelated so it can be reduced by multiple samples. The AD9826 data sheet lists a cross-talk between channels of 72 dB, which is not good enough to run individual CCD amplifiers through different channels, and we have elected to use one channel of the AD9826 per CCD amplifier.

We do not use the conventional technique of dual slope integration to reduce bandwidth and noise, nor do we use the CDS function in the AD9826. Instead, we digitize many samples on every pixel (typically four per pedestal and four per signal) and do digital arithmetic in the FPGA: sum four signal samples, subtract four pedestal samples, divide by four. The oscilloscope trace in Fig. 6 shows an example of a video signal and the four samples we make of the pedestal and signal levels. This serves both to reduce the A/D noise to 2 ADU as well as averaging down the detector noise. We have tested the noise performance of the controller using a low-noise CCID20 which has about 2.1 e- noise when read out using an SDSU controller at high gain and 160 kpix/sec. The timing illustrated in Fig. 6 achieves 3.8 e- read noise at a pixel rate of 530 kpix/sec. We expect that we can do improve this by steering the samples between clock transitions and careful bandwidth tuning of the stages leading up to the A/D. It is also possible to use the FPGA to weigh different samples for additional improvement.

Figure 6. This oscilloscope trace illustrates how we take 4 samples on the video pedestal and four on the signal of each pixel. The resulting samples are digitized and added, subtracted, and scaled by 4 by the FPGA before delivery to the pixelserver.

One of the real strengths of the Pan-STARRS project is that the development of detectors, controller, and software are all happening in conjunction and synergistically. For example, we will be transitioning to a 2-phase serial register to reduce the clock feedthrough and produce faster and cleaner video. We are nearing completion of the design of a revised controller and preamp board, and expect to implement them in time for TC3 and PS1 in January 2006.

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