In order to achieve a high level of compatibility with modern bus structures, the PCI bus model has been used as a base for reference due to its presence at the CPU board level, as well as in different 'industrial' structures like the VME bus and the CPCI. It was thus possible to cover a wide range of bus standards with the construction of the two basic detector host-adapters shown in Fig. 1:
• the PCI model, covering low-cost PC based systems, and
• the PMC model, covering more professional structures like CPCI and VME
Both systems are built around a standard AMCC PCI bus adapter and are served by a Motorola DSP53301 processor acting as a programmable clock sequencer. The processor is compatible with the existing off-line software for clock waveforms design and run-length encoding. Clocks produced by the DSP at a stable tick time of 50 nSec are serialized, sent to the remote controller board and de-serialized. The same is done for commands and operands, so that the remote electronics are completely passive and a unique system clock is used at 40 Mhz on the remote head.
The more complex PMC module adds the presence of a large FPGA array, custom programmable from the host computer, to implement fast algorithms on the detector data flow.
The DSP 56301 and the FPGA have their own memory for data and programs; both can use the output channel to the remote unit for commands and readout sequences. This means that both can be used as clock-sequence generators. Conversely, the input fast channel for data can be used only by the FPGA. It is then possible to process data from the detector 'on the fly' using wired functions on the FPGA (co-adding, computation of event centroids, tracking of objects, etc.). The configuration of the FPGA can be changed so the controller interface can be remotely reprogrammed by downloading the micro-code into the dedicated memory from the host-
computer. Both boards are provided with an opto-coupled I/O port acting as a general services port or, if required, as a synchronization link for expanded systems (see Fig. 2).
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