The system uses an Aletera Cyclon family FPGA. All of the design is performed by the Quartus II FPGA development software from Altera. The Quartus II design software provides the most advanced suite of tools for system-level design, embedded software programming, FPGA and CPLD design, synthesis, place-and-route, verification, and device programming.
The top level (see Fig. 3) consists of user logic, NIOS embedded processor, master clock and control signals. In the user logic all of the CCD clocks and control signals are produced. This is accomplished by VHDL.
Since all of the signals produced by a single FPGA, simulation can be used in the design stage at any time. Most of the design should be simulated multiple times and adjusted carefully. In our case we can check all the waveforms in the computer. Any mistake can be found and corrected in the design stage. After completing these components, an oscilloscope will determine if the simulator had correct timing for all waveforms.
Cyclone devices have up to two enhanced Phase-Locked Loops (PLLs). They provide advanced clock management capabilities such as frequency synthesis, programmable phase shift, external clock output, programmable duty cycle, lock detection, and high-speed differential support on the input and output clocks. The master clock of AACAS uses PLLs and can supply very flexible and accurate clocks, reducing the difficulty of the system design. The control signals including ADC control signals, readout modes, control signals, CDS and gain control signals.
SOPC (System On a Programmable Chip) Builder is an automated system development tool that dramatically simplifies the task of creating high-performance SOPC designs. SOPC Builder is included as part of Quartus II software products. The NIOS embedded processor is designed with this tool.
When the design of all the above parts is completed, the Quartus software compiles the project and then downloads the programming code into the FPGA device.
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