Analogtodigital converters

Analog-to-digital (A/D) converters are not really a subject for this book. However, the output pixel values from a CCD (digital numbers stored in a computer) are completely determined by the method used to sample the charge on a pixel and how that sampling is converted into a digital number or data number to be stored in computer memory. A/D converters for use in CCDs, including linear and logarithmic types, have been reviewed in Opal (1988). The output from each pixel in a CCD must be examined by electronic means in order to determine how much charge has been collected during a given integration and to convert that charge value into a digital number.

As each packet is clocked out of the CCD output register, it is passed through an on-chip amplifier circuit built directly into the CCD substrate. Next, the packet passes into an external low-noise solid state amplifier, to increase the signal strength, followed by input into the integrating amplifier. The output from the integrating amplifier is then sent directly into an A/D converter, which converts the analog voltage into a digital number to be stored in computer memory. The electronic circuitry just described, minus the on-chip amplifier, is often called the CCD head electronics and is usually located in a box very near or attached directly to the CCD dewar itself.

To measure the voltage of each charge packet, in preparation for conversion into a digital number, a difference measurement is performed between the reset voltage and the sum of the charge packet plus a constant reset voltage. A well-regulated constant voltage source is needed in this step to supply the voltage to the electronics of the inverting plus integrating amplifier circuits. An integrating capacitor, connected across the integrating amplifier, first samples the reset voltage passed through the inverting amplifier for typically 20 ^s. A single pixel charge packet is then passed through the non-inverting amplifier with the output being sampled by the same integrating capacitor for the same time period. Equal time sampling is critical as one has to worry about charge decay in the capacitor. Generally, however, the RC time constant for the capacitor is of the order of a few seconds, while the sampling is a few tens of microseconds. Both signals sampled by the capacitor contain the reset voltage, but only one has the pixel charge packet. Thus the difference formed by the two opposite signed voltages provides a very good estimate of the actual charge level within the sampled pixel. The value of the reset voltage, whatever it may be, is completely eliminated by this differencing. This technique, for sampling the amount of charge within each pixel, is used in almost all current day CCDs and is called correlated double sampling (CDS). Details of the CDS process and some CDS variations such as the dual slope process and triple correlated sampling are discussed in Janesick & Elliott (1992), Opal (1988), Joyce (1992), and McLean (1997b). CMOS devices, as discussed above, can use logic built directly onto each pixel to perform this conversion and provide a digital output directly from the CMOS device.

The assignment of an output digital number to the value of the charge packet from each pixel is the job of the A/D converter. The charge stored in each pixel has an analog value (discrete only at the 1 electron level1) and the process of CDS decides how to assign each pixel's charge packet to a specific data number (DN) or analog-to-digital unit (ADU) (Merline & Howell, 1995). As briefly mentioned in Chapter 1, this assignment is dependent on the device gain as follows.

If the gain for a CCD has a value of 10 electrons/ADU, the digitization process tries to divide each pixel's charge packet into units of 10 electrons each, assigning 1 ADU to each 10 electrons it measures. If, after division, there are fewer than 10 electrons left then the remaining charge is not counted and is lost and therefore unknown to the output pixel value. We will see (Section 3.8 and Howell & Merline (1991)) that the gain of a device can have a great effect on its ability to provide good photometric information.

The ultimate readout speed of a given CCD depends on how fast the process of pixel examination and A/D conversion can take place. Modern large-format devices can, and often do, use two or four output amplifiers during readout (one at each device corner) providing a faster overall readout time. However, such readout schemes can introduce systematic offsets between each quadrant of the CCD owing to slight differences in the four output amplifiers and associated electronics. This effect is often seen in images produced by large-format CCDs, where one or more quadrants will show an apparently different background level. An additional common effect seen in many large format CCDs and mosaic CCD imagers is A/D ghosting. If a single CCD or two CCDs in a mosaic share an A/D converter, a bright (usually saturated) star imaged in one part of a CCD (or one CCD in a mosaic) can produce a low level, ghost image in the other CCD region sharing the A/D. This ghosting occurs as the saturated star's charge overwhelms the capacitor during the reset

1 Even though CCDs are called digital devices, the output from each pixel is really an analog voltage that must be measured and digitized by the A/D converter.

cycle and leaves residual charge. This charge is added to the pixels from the shared region producing the ghost image.

The readout speed of a CCD is also related to the number of bits of precision desired (A/D converters with fewer bits of precision work faster than those with more bits) and the acceptable readout noise level (faster pixel readout increases the introduced noise level). Current ultra-low-noise A/D converters can distinguish the reference value from the collected charge in a given pixel at the 2 to 4 electron level.

Let us examine A/D converters in a bit more detail. As CCDs become better produced integrated circuits with less noise and better charge clocking and on-chip parts such as the output amplifiers are made smaller (less thermal noise), the overall noise of a device becomes very low, perhaps 1-2 electrons. At this level, very good modern systems are discovering that the linearity of the A/D converter is now of increased concern. A 1% linearity value is often quoted for CCDs and often observers expect no less from a CCD. But what is the reality of the A/D linearity for a system one is likely to use?

Readout speed has increased, as mentioned above, with an additional reason being the size of the A/D converter and the speed at which it can, well, convert. This entire process is called digitization. CCD controller technology in the 1990s, such as a Leach (SDSU) controller, readout CCDs at a rate of 200 kHz while today's modern controllers A/D convert at rates as high as 800kHz to 1 MHz. Additionally, present day A/D converters of high quality can be obtained that use 18 bits, not a mere 16 bits. We will see in the next chapter that this is of great benefit.

To complete the efficiency and speed we desire in modern CCD systems, CCD controllers (i.e., the hardware that controls the electronic functions of a CCD) must be quite complex in design, highly versatile in their abilities, and yet simple in their use. Readout rates for CCDs are a prime concern as larger format chips may require excessively long readout times. Controllers such as those developed by San Diego State University (Leach, 1995) can read pixels out at a maximum rate of 10 ^s/pixel, but a practical rate of near 50 ^s/pixel is generally used to keep the read noise to a minimum (<10 electrons/pixel/read). Even at these seemingly fast rates (20 kHz), a 2048 x 2048 CCD, containing over four million pixels, takes over 200 seconds to readout the full frame. Requirements for new generation CCDs are even more stringent. A modern CCD controller must readout fast while keeping the read noise below 5 electrons. Complex readout schemes, real-time feedback modes, and other CCD observing strategies mean that modern controllers must also provide the ability to support various observing modes and run various types of CCDs (often including IR arrays). Most controllers under

Fig. 2.10. A photograph of a modern CCD controller. The MONSOON CCD controller is being developed at the NOAO for use with optical CCDs, OTCCDs, and IR arrays. The photograph shows the three component circuit boards and the chassis into which the boards are placed. The three boards are (left to right) a clock and bias board, a master control board, which produces the clocking for integration and readout, and an 8-channel CCD acquisition board, which contains the A/Ds.

Fig. 2.10. A photograph of a modern CCD controller. The MONSOON CCD controller is being developed at the NOAO for use with optical CCDs, OTCCDs, and IR arrays. The photograph shows the three component circuit boards and the chassis into which the boards are placed. The three boards are (left to right) a clock and bias board, a master control board, which produces the clocking for integration and readout, and an 8-channel CCD acquisition board, which contains the A/Ds.

development at present have the ability to "plug in" a CPU directly on the controller board and off-load many of the CCD control and readout functions from the observing computer. This allows on-board logic for fast control and readout while keeping the higher level user computer free for real-time data examination and analysis. An example of a modern CCD controller, MONSOON, is shown in Figure 2.10.

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